Hi Peter and all, This patch series adds ARM Cortex R5 processor support. The PMSAv7 MPU is implemented. Two R5s are added to the Xilinx ZynqMP SoC.
Changed since v1: Addressed PMM and Alistair reviews (see indiv. patches) Adding prepatory refactorings to target-arm (new patches) - TLBTR VMSA conditional (1) - V7MP CP regs VMSA conditional (2) - Refactor get_phys_addr FSR return path (4) - Add MPUIR.U config (5) - Improved cpu configurability around MPUs (6-7) Regards, Peter Peter Crosthwaite (13): arm: Do not define TLBTR in PMSA systems arm: Don't add v7mp registers in MPU systems arm: helper: Factor out CP regs common to [pv]msa arm: Refactor get_phys_addr FSR return mechanism arm: Implement uniprocessor with MP config arm: Add has-mpu property target-arm/helper.c: define MPUIR register arm: helper: rename get_phys_addr_mpu target-arm: Add registers for PMSAv7 target-arm: Implement PMSAv7 MPU target-arm: Add support for Cortex-R5 arm: xlnx-zynqmp: Preface CPU variables with "apu" arm: xlnx-zynqmp: Add 2xCortexR5 CPUs hw/arm/xlnx-ep108.c | 2 +- hw/arm/xlnx-zynqmp.c | 53 ++++-- include/hw/arm/xlnx-zynqmp.h | 6 +- target-arm/cpu-qom.h | 8 + target-arm/cpu.c | 69 +++++++ target-arm/cpu.h | 11 ++ target-arm/helper.c | 439 +++++++++++++++++++++++++++++++++++-------- target-arm/internals.h | 3 +- target-arm/machine.c | 35 ++++ target-arm/op_helper.c | 11 +- 10 files changed, 533 insertions(+), 104 deletions(-) -- 2.4.3.3.g905f831
