Hi Peter and all, This patch series adds ARM Cortex R5 processor support. The PMSAv7 MPU is implemented. Two R5s are added to the Xilinx ZynqMP SoC.
Changed since v2: Rebased (early patches merged) Added boot CPU selection. Addressed PMM review (see indiv. patches) Changed since v1: Addressed PMM and Alistair reviews (see indiv. patches) Adding prepatory refactorings to target-arm (new patches) - TLBTR VMSA conditional (1) - V7MP CP regs VMSA conditional (2) - Refactor get_phys_addr FSR return path (4) - Add MPUIR.U config (5) - Improved cpu configurability around MPUs (6-7) Regards, Peter Peter Crosthwaite (7): target-arm/helper.c: define MPUIR register target-arm: Add registers for PMSAv7 target-arm: Implement PMSAv7 MPU target-arm: Add support for Cortex-R5 arm: xlnx-zynqmp: Preface CPU variables with "apu" arm: xlnx-zynqmp: Add boot-cpu property arm: xlnx-zynqmp: Add 2xCortexR5 CPUs hw/arm/xlnx-ep108.c | 2 +- hw/arm/xlnx-zynqmp.c | 79 +++++++++++-- include/hw/arm/xlnx-zynqmp.h | 9 +- target-arm/cpu-qom.h | 2 + target-arm/cpu.c | 62 ++++++++++ target-arm/cpu.h | 11 ++ target-arm/helper.c | 274 +++++++++++++++++++++++++++++++++++++++++-- target-arm/machine.c | 34 ++++++ 8 files changed, 449 insertions(+), 24 deletions(-) -- 2.4.3.3.g905f831
