On Mon, Jun 29, 2015 at 1:11 PM, Jean-Christophe Dubois <j...@tribudubois.net> wrote: > This is to prepare to accomodate the SOC requirements. >
Same but only 2, one for style, one for headering. Regards, Peter > Signed-off-by: Jean-Christophe Dubois <j...@tribudubois.net> > --- > > Changes since v1: > * not present on v1 > > Changes since v2: > * not present on v2 > > Changes since v3: > * not present on v3 > > Changes since v4: > * not present on v4 > > Changes since v5: > * not present on v5 > > Changes since v6: > * not present on v6 > > Changes since v7: > * Splited the i.MX AVIC emulator into a header file and a source file > > hw/intc/imx_avic.c | 56 > +++++++++------------------------------------- > include/hw/intc/imx_avic.h | 56 > ++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 66 insertions(+), 46 deletions(-) > create mode 100644 include/hw/intc/imx_avic.h > > diff --git a/hw/intc/imx_avic.c b/hw/intc/imx_avic.c > index e48f66c..96c376b 100644 > --- a/hw/intc/imx_avic.c > +++ b/hw/intc/imx_avic.c > @@ -7,6 +7,7 @@ > * Copyright (c) 2008 OKL > * Copyright (c) 2011 NICTA Pty Ltd > * Originally written by Hans Jiang > + * Updated by Jean-Christophe Dubois <j...@tribudubois.net> > * > * This code is licensed under the GPL version 2 or later. See > * the COPYING file in the top-level directory. > @@ -14,16 +15,14 @@ > * TODO: implement vectors. > */ > > -#include "hw/hw.h" > -#include "hw/sysbus.h" > -#include "qemu/host-utils.h" > +#include "hw/intc/imx_avic.h" > > #define DEBUG_INT 1 > #undef DEBUG_INT /* comment out for debugging */ > > #ifdef DEBUG_INT > #define DPRINTF(fmt, args...) \ > -do { printf("imx_avic: " fmt , ##args); } while (0) > +do { printf("%s: " fmt , TYPE_IMX_AVIC, ##args); } while (0) > #else > #define DPRINTF(fmt, args...) do {} while (0) > #endif > @@ -35,46 +34,13 @@ do { printf("imx_avic: " fmt , ##args); } while (0) > #define DEBUG_IMPLEMENTATION 1 > #if DEBUG_IMPLEMENTATION > # define IPRINTF(fmt, args...) \ > - do { fprintf(stderr, "imx_avic: " fmt, ##args); } while (0) > + do { fprintf(stderr, "%s: " fmt, TYPE_IMX_AVIC, ##args); } while (0) > #else > # define IPRINTF(fmt, args...) do {} while (0) > #endif > > -#define IMX_AVIC_NUM_IRQS 64 > - > -/* Interrupt Control Bits */ > -#define ABFLAG (1<<25) > -#define ABFEN (1<<24) > -#define NIDIS (1<<22) /* Normal Interrupt disable */ > -#define FIDIS (1<<21) /* Fast interrupt disable */ > -#define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */ > -#define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */ > -#define NM (1<<18) /* Normal interrupt mode */ > - > - > -#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4) > -#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD) > - > -#define TYPE_IMX_AVIC "imx_avic" > -#define IMX_AVIC(obj) \ > - OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC) > - > -typedef struct IMXAVICState { > - SysBusDevice parent_obj; > - > - MemoryRegion iomem; > - uint64_t pending; > - uint64_t enabled; > - uint64_t is_fiq; > - uint32_t intcntl; > - uint32_t intmask; > - qemu_irq irq; > - qemu_irq fiq; > - uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */ > -} IMXAVICState; > - > static const VMStateDescription vmstate_imx_avic = { > - .name = "imx-avic", > + .name = TYPE_IMX_AVIC, > .version_id = 1, > .minimum_version_id = 1, > .fields = (VMStateField[]) { > @@ -88,8 +54,6 @@ static const VMStateDescription vmstate_imx_avic = { > }, > }; > > - > - > static inline int imx_avic_prio(IMXAVICState *s, int irq) > { > uint32_t word = irq / PRIO_PER_WORD; > @@ -249,7 +213,7 @@ static uint64_t imx_avic_read(void *opaque, > return 0x4; > > default: > - IPRINTF("imx_avic_read: Bad offset 0x%x\n", (int)offset); > + IPRINTF("%s: Bad offset 0x%x\n", __func__, (int)offset); > return 0; > } > } > @@ -261,12 +225,12 @@ static void imx_avic_write(void *opaque, hwaddr offset, > > /* Vector Registers not yet supported */ > if (offset >= 0x100 && offset <= 0x2fc) { > - IPRINTF("imx_avic_write to vector register %d ignored\n", > + IPRINTF("%s to vector register %d ignored\n", __func__, > (unsigned int)((offset - 0x100) >> 2)); > return; > } > > - DPRINTF("imx_avic_write(0x%x) = %x\n", > + DPRINTF("%s(0x%x) = %x\n", __func__, > (unsigned int)offset>>2, (unsigned int)val); > switch (offset >> 2) { > case 0: /* Interrupt Control Register, INTCNTL */ > @@ -341,7 +305,7 @@ static void imx_avic_write(void *opaque, hwaddr offset, > return; > > default: > - IPRINTF("imx_avic_write: Bad offset %x\n", (int)offset); > + IPRINTF("%s: Bad offset %x\n", __func__, (int)offset); > } > imx_avic_update(s); > } > @@ -370,7 +334,7 @@ static int imx_avic_init(SysBusDevice *sbd) > IMXAVICState *s = IMX_AVIC(dev); > > memory_region_init_io(&s->iomem, OBJECT(s), &imx_avic_ops, s, > - "imx_avic", 0x1000); > + TYPE_IMX_AVIC, 0x1000); > sysbus_init_mmio(sbd, &s->iomem); > > qdev_init_gpio_in(dev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS); > diff --git a/include/hw/intc/imx_avic.h b/include/hw/intc/imx_avic.h > new file mode 100644 > index 0000000..1645ba6 > --- /dev/null > +++ b/include/hw/intc/imx_avic.h > @@ -0,0 +1,56 @@ > +/* > + * i.MX31 Vectored Interrupt Controller > + * > + * Note this is NOT the PL192 provided by ARM, but > + * a custom implementation by Freescale. > + * > + * Copyright (c) 2008 OKL > + * Copyright (c) 2011 NICTA Pty Ltd > + * Originally written by Hans Jiang > + * Updated by Jean-Christophe Dubois <j...@tribudubois.net> > + * > + * This code is licensed under the GPL version 2 or later. See > + * the COPYING file in the top-level directory. > + * > + * TODO: implement vectors. > + */ > +#ifndef IMX_AVIC_H > +#define IMX_AVIC_H > + > +#include "hw/sysbus.h" > + > +#define TYPE_IMX_AVIC "imx.avic" > +#define IMX_AVIC(obj) OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC) > + > +#define IMX_AVIC_NUM_IRQS 64 > + > +/* Interrupt Control Bits */ > +#define ABFLAG (1<<25) > +#define ABFEN (1<<24) > +#define NIDIS (1<<22) /* Normal Interrupt disable */ > +#define FIDIS (1<<21) /* Fast interrupt disable */ > +#define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */ > +#define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */ > +#define NM (1<<18) /* Normal interrupt mode */ > + > + > +#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4) > +#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD) > + > +typedef struct { > + /*< private >*/ > + SysBusDevice parent_obj; > + > + /*< public >*/ > + MemoryRegion iomem; > + uint64_t pending; > + uint64_t enabled; > + uint64_t is_fiq; > + uint32_t intcntl; > + uint32_t intmask; > + qemu_irq irq; > + qemu_irq fiq; > + uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */ > +} IMXAVICState; > + > +#endif // IMX_AVIC_H > -- > 2.1.4 > >