On 2015-06-30 16:33, Yongbok Kim wrote: > In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF > and CACHE instructions have 9 bits offsets. > > Signed-off-by: Yongbok Kim <yongbok....@imgtec.com> > --- > disas/mips.c | 12 ++++++------ > 1 files changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net> -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurel...@aurel32.net http://www.aurel32.net
