On 30/06/2015 16:33, Yongbok Kim wrote: > In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF > and CACHE instructions have 9 bits offsets. > > Signed-off-by: Yongbok Kim <yongbok....@imgtec.com> > --- > disas/mips.c | 12 ++++++------ > 1 files changed, 6 insertions(+), 6 deletions(-)
Applied this and the other fix "target-mips: fix to clear MSACSR.Cause" to mips-next, thanks. Leon
