Add IVRS table for AMD IO MMU. Also reverve MMIO
region for IO MMU via ACPI
Signed-off-by: David Kiarie <davidkiar...@gmail.com>
---
hw/i386/acpi-build.c | 96 +++++++++++++++++++++++++++++++++++++++++++++
include/hw/acpi/acpi-defs.h | 55 ++++++++++++++++++++++++++
2 files changed, 151 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 78758e2..5a5d594 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -52,6 +52,7 @@
#include "hw/pci/pci_bus.h"
#include "hw/pci-host/q35.h"
#include "hw/i386/intel_iommu.h"
+#include "hw/i386/amd_iommu.h"
#include "hw/timer/hpet.h"
#include "hw/acpi/aml-build.h"
@@ -2424,6 +2425,88 @@ build_dmar_q35(GArray *table_data, GArray *linker)
}
static void
+amd_iommu_acpi_set_flag(uint8_t *value, uint64_t flag)
+{
+ uint64_t newvalue = *value | flag;
+ *(uint64_t *)value = newvalue;
+}
+
+static void
+amd_iommu_acpi_set_feature(uint64_t *value, uint64_t feature)
+{
+ uint64_t newvalue = *value | feature;
+ *value = newvalue;
+}
+
+static void
+build_amd_iommu(GArray *table_data, GArray *linker)
+{
+ int iommu_start = table_data->len;
+ bool iommu_ambig;
+ uint64_t host_width = (AMD_IOMMU_HOST_ADDRESS_WIDTH << 8);
+
+ AcpiAMDIOMMUIVRS *ivrs;
+ AcpiAMDIOMMUHardwareUnit *iommu;
+
+ /* IVRS definition */
+ ivrs = acpi_data_push(table_data, sizeof(*ivrs));
+ ivrs->revision = ACPI_IOMMU_IVRS_TYPE;
+ ivrs->length = (sizeof(*ivrs) + sizeof(*iommu));
+ ivrs->v_common_info = host_width;
+
+ AMDIOMMUState *s = (AMDIOMMUState *)object_resolve_path_type("",
+ TYPE_AMD_IOMMU_DEVICE, &iommu_ambig);
+
+ /* IVDB definition */
+ iommu = acpi_data_push(table_data, sizeof(*iommu));
+ if (!iommu_ambig) {
+ iommu->type = 0x10;
+ /* IVHD flags */
+ amd_iommu_acpi_set_flag(&iommu->flags, IVHD_HT_TUNEN);
+ amd_iommu_acpi_set_flag(&iommu->flags, IVHD_PPRSUP);
+ amd_iommu_acpi_set_flag(&iommu->flags, IVHD_IOTLBSUP);
+ amd_iommu_acpi_set_flag(&iommu->flags, IVHD_ISOC);
+ amd_iommu_acpi_set_flag(&iommu->flags, IVHD_PREFSUP);
+
+ iommu->length = sizeof(*iommu);
+ iommu->device_id = PCI_DEVICE_ID_RD890_IOMMU;
+ iommu->capability_offset = s->capab_offset;
+ iommu->mmio_base = s->mmio.addr;
+ fprintf(stderr, "MMIO addr acpi %lx", s->mmio.addr);
+
+ iommu->pci_segment = cpu_to_le16(0);
+ iommu->interrupt_info = cpu_to_le16(0);
+
+ /* EFR features */
+ amd_iommu_acpi_set_feature(&iommu->efr_register, IVHD_EFR_GTSUP);
+ amd_iommu_acpi_set_feature(&iommu->efr_register, IVHD_EFR_HATS);
+ amd_iommu_acpi_set_feature(&iommu->efr_register, IVHD_EFR_GATS);
+
+ /* device entries */
+ memset(iommu->dev_entries, 0, 20);
+
+ /* Add device flags here */
+ iommu->dev_entries[12] = 3;
+ iommu->dev_entries[16] = 4;
+ iommu->dev_entries[17] = 0xff;
+ iommu->dev_entries[18] = 0xff;
+ }
+
+ build_header(linker, table_data, (void *)(table_data->data + iommu_start),
+ "IVRS", table_data->len - iommu_start, 1, NULL);
+}
+
+static bool acpi_has_amd_iommu(void)
+{
+ bool ambiguous;
+ Object *amd_iommu;
+
+ amd_iommu = object_resolve_path_type("", TYPE_AMD_IOMMU_DEVICE,
+ &ambiguous);
+ return amd_iommu && !ambiguous;
+}
+
+static void
build_dsdt(GArray *table_data, GArray *linker,
AcpiPmInfo *pm, AcpiMiscInfo *misc)
{
@@ -2481,6 +2564,14 @@ build_dsdt(GArray *table_data, GArray *linker,
build_q35_pci0_int(dsdt);
}
+ /* AMD IOMMU */
+ if (acpi_has_amd_iommu()) {
+ sb_scope = aml_scope("_SB");
+ aml_append(sb_scope,
+ aml_operation_region("AMDV", AML_SYSTEM_MEMORY, IOMMU_BASE_ADDR,
+ 16*1024));
+ }
+
build_cpu_hotplug_aml(dsdt);
build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
pm->mem_hp_io_len);
@@ -2691,6 +2782,11 @@ void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables
*tables)
build_dmar_q35(tables_blob, tables->linker);
}
+ if (acpi_has_amd_iommu() && !acpi_has_iommu()) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_amd_iommu(tables_blob, tables->linker);
+ }
+
if (acpi_has_nvdimm()) {
nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
}
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index c7a03d4..a161358 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -570,4 +570,59 @@ typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
/* Masks for Flags field above */
#define ACPI_DMAR_INCLUDE_PCI_ALL 1
+/* IVRS constants */
+#define ACPI_IOMMU_HARDWAREUNIT_TYPE 0x10
+#define ACPI_IOMMU_IVRS_TYPE 0x1
+#define AMD_IOMMU_HOST_ADDRESS_WIDTH 39UL
+
+/* AMD IOMMU IVRS table */
+struct AcpiAMDIOMMUIVRS {
+ ACPI_TABLE_HEADER_DEF
+ uint32_t v_common_info; /* common virtualization information */
+ uint64_t reserved; /* reserved */
+} QEMU_PACKED;
+typedef struct AcpiAMDIOMMUIVRS AcpiAMDIOMMUIVRS;
+
+/* flags in the IVHD headers */
+#define IVHD_HT_TUNEN (1UL << 0)
+#define IVHD_PASS_PW (1UL << 1)
+#define IVHD_RESPASS_PW (1UL << 2)
+#define IVHD_ISOC (1UL << 3)
+#define IVHD_IOTLBSUP (1UL << 4)
+#define IVHD_COHERENT (1UL << 5)
+#define IVHD_PREFSUP (1UL << 6)
+#define IVHD_PPRSUP (1UL << 7)
+
+/* features in the IVHD headers */
+#define IVHD_EFR_HATS 48
+#define IVHD_EFR_GATS 48
+#define IVHD_EFR_MSI_NUM
+#define IVHD_EFR_PNBANKS
+#define IVHD_EFR_PNCOUNTERS
+#define IVHD_EFR_PASMAX
+#define IVHD_EFR_HESUP (1UL << 7)
+#define IVHD_EFR_GASUP (1UL << 6)
+#define IVHD_EFR_IASUP (1UL << 5)
+#define IVHD_EFR_GLXSUP (3UL << 3)
+#define IVHD_EFR_GTSUP (1UL << 2)
+#define IVHD_EFR_NXSUP (1UL << 1)
+#define IVHD_EFR_XTSUP (1UL << 0)
+
+/* IVDB type 10h */
+struct AcpiAMDIOMMUHardwareUnit {
+ uint8_t type;
+ uint8_t flags;
+ uint16_t length;
+ uint16_t device_id;
+ uint16_t capability_offset;
+ uint64_t mmio_base;
+ uint16_t pci_segment;
+ uint16_t interrupt_info;
+ uint32_t features;
+ uint64_t efr_register;
+ uint64_t reserved;
+ uint8_t dev_entries[20];
+} QEMU_PACKED;
+typedef struct AcpiAMDIOMMUHardwareUnit AcpiAMDIOMMUHardwareUnit;
+
#endif
--
2.1.4
