On 2016-01-14 16:39, Michael S. Tsirkin wrote: > On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote: >> On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin <m...@redhat.com> wrote: >>> On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote: >>>> Add IVRS table for AMD IO MMU. Also reverve MMIO >>> >>> reserve? >> >> Yeah, typo. >> >>> >>>> region for IO MMU via ACPI >>> >>> >>> It does not look like you reserve anything. >>> >>> Pls add a link to hardware spec (in >>> the device implementation) so we can check >>> what does real hardware do. >>> >>> If this is it: >>> http://developer.amd.com/wordpress/media/2012/10/488821.pdf >>> >>> then the way that works seems to be by guest >>> programming the MMIO base. >>> We should do the same: patch seabios and EFI to do this. >> >> Yes, that's the spec. >> >> We thought this could be possible via ACPI (without patching BIOS ), no ? > > I don't see how. We should do it the way it happens on real hardware. >
Doesn't Seabios retrieve certain ACPI fragments from QEMU via a pv-interface by now? Anyway, the question remains where this address comes from: The BIOS, which then writes it into some hw config register and reports it in addition via ACPI or the hardware (hard-wired). Jan
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