Hi all, I recall I saw IVRS filling code in the coreboot for one of the boards supported. David, you may want to have a look there.
Valentine (from the phone) On Jan 14, 2016 9:29 PM, "Kevin O'Connor" <ke...@koconnor.net> wrote: > On Thu, Jan 14, 2016 at 12:09:46PM +0200, Michael S. Tsirkin wrote: > > On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote: > > > Add IVRS table for AMD IO MMU. Also reverve MMIO > > > > reserve? > > > > > region for IO MMU via ACPI > > > > > > It does not look like you reserve anything. > > > > Pls add a link to hardware spec (in > > the device implementation) so we can check > > what does real hardware do. > > > > If this is it: > > http://developer.amd.com/wordpress/media/2012/10/488821.pdf > > > > then the way that works seems to be by guest > > programming the MMIO base. > > We should do the same: patch seabios and EFI to do this. > > A similar question - how does a typical factory BIOS select which > address to set as the MMIO base? Is it generally hard-coded or is it > allocated from a range in some way? > > -Kevin >
