Hi Richard, Awesome, thanks for looking at these patches again :-)
On Tue, Feb 09, 2016 at 09:39:50PM +1100, Richard Henderson wrote:
> +#if !use_mips32r6_instructions
> + { INDEX_op_muls2_i64, { "r", "r", "rZ", "rZ" } },
> + { INDEX_op_mulu2_i64, { "r", "r", "rZ", "rZ" } },
> +#endif
this...
> +#define TCG_TARGET_HAS_mulu2_i64 1
> +#define TCG_TARGET_HAS_muls2_i64 1
and this are inconsistent for r6:
Missing op definition for mulu2_i64
Missing op definition for muls2_i64
/work/mips/qemu/main/tcg/tcg.c:1253: tcg fatal error
It gets further (to the point of seg faulting - looking into it) with
this fixup:
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 374d80374021..fa9cd4ab296a 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -145,8 +145,8 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
-#define TCG_TARGET_HAS_mulu2_i64 1
-#define TCG_TARGET_HAS_muls2_i64 1
+#define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)
+#define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muluh_i64 1
#define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_TARGET_HAS_ext32s_i64 1
Cheers
James
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