On Tue, 9 Feb 2016, Richard Henderson wrote: > > So to be correct + efficient, it should only put the nop in if the next > > generated instruction is a CTI. I imagine that would be a bit messy / > > fragile, but maybe doable? I haven't looked too deeply. > > Ouch, I didn't notice this about these insns. > > I suppose this might be rare enough that it's still worth thinking about. Off > the top of my head I can't think of any way to save extra state, but perhaps > just looking back at the previous insn's major opcode is enough when emitting > any forbidden insn.
FWIW I think this is a reasonable approach, applying to the regular MIPS ISA where the size of the instruction word is fixed so you can look at the preceding instruction in a reproducible manner. And in the microMIPSr6 ISA there are no forbidden slots, so no issue there in the first place. Maciej
