On 29.02.2016 19:18, Peter Maydell wrote: > Starting with the ARMv7 Virtualization Extensions, the A32 and T32 > instruction sets provide instructions "MSR (banked)" and "MRS > (banked)" which can be used to access registers for a mode other > than the current one: > * R<m>_<mode> > * ELR_hyp > * SPSR_<mode> > > Implement the missing instructions.
Likely, there is no disassembling support in QEMU for these instructions as well. Are you going to add it? Best regards, Sergey > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > We don't support EL2 yet, but you can get at these on a v8 CPU in > 32-bit EL1 if EL3 is enabled. Obviously there's not going to be much > 32-bit EL1 code out there that uses the insns though, as it wouldn't > work on v7 if it did...
