On 03/06/16 23:43, Peter Maydell wrote: > On 3 June 2016 at 20:49, Sergey Fedorov <serge.f...@gmail.com> wrote: >> I'm not so sure about acq/rel flags. Is there any architecture which has >> explicit acq/rel barriers? I suppose acq/rel memory access instructions >> are always load-link and store-conditional and thus rely on exclusive >> memory monitor to support that "conditional" behaviour. > This doesn't sound right (at least not for ARM). You can have > load-acquire and store-release insns which aren't exclusives, > you can have exclusives which aren't acq/rel, and you can > have accesses which are both exclusives and acq/rel (and > just to complete the set, obviously there are accesses which > are neither). The exclusive semantics require the monitor, but > acq/rel is just an ordering constraint (sort of like an implicit > barrier, but not quite).
Thanks for clarifying this, Peter. Regards, Sergey
