On Mon, Jun 6, 2016 at 11:49 AM, Sergey Fedorov <serge.f...@gmail.com> wrote: > On 06/06/16 18:47, Pranith Kumar wrote: >> On Mon, Jun 6, 2016 at 11:44 AM, Sergey Fedorov <serge.f...@gmail.com> wrote: >>> On 03/06/16 21:27, Pranith Kumar wrote: >>>> On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson <r...@twiddle.net> wrote: >>>>> What if we have tcg_canonicalize_memop (or some such) split off the >>>>> barriers >>>>> into separate opcodes. E.g. >>>>> >>>>> MO_BAR_LD_B = 32 // prevent earlier loads from crossing current op >>>>> MO_BAR_ST_B = 64 // prevent earlier stores from crossing current op >>>>> MO_BAR_LD_A = 128 // prevent later loads from crossing current op >>>>> MO_BAR_ST_A = 256 // prevent later stores from crossing current op >>>>> MO_BAR_LDST_B = MO_BAR_LD_B | MO_BAR_ST_B >>>>> MO_BAR_LDST_A = MO_BAR_LD_A | MO_BAR_ST_A >>>>> MO_BAR_MASK = MO_BAR_LDST_B | MO_BAR_LDST_A >>>>> >>>>> // Match Sparc MEMBAR as the most flexible host. >>>>> TCG_BAR_LD_LD = 1 // #LoadLoad barrier >>>>> TCG_BAR_ST_LD = 2 // #StoreLoad barrier >>>>> TCG_BAR_LD_ST = 4 // #LoadStore barrier >>>>> TCG_BAR_ST_ST = 8 // #StoreStore barrier >>>>> TCG_BAR_SYNC = 64 // SEQ_CST barrier >>>> I really like this format. I would also like to add to the frontend: >>>> >>> Actually, the acquire barrier is a combined load-load + load-store >>> barrier; and the release barrier is a combo of load-store + store-store >>> barriers. >>> >> All the above are two-way barriers. Acquire/Release are one-way >> barriers. So we cannot combine the above to get acquire/release >> semantics without being conservative. > > Do you mean *barriers* or *memory access* operations implying memory > ordering?
I meant the latter. I know no arch which has acquire/release barriers. Sorry for the confusion. Thanks, -- Pranith
