Signed-off-by: Artyom Tarasenko <atar4q...@gmail.com>
---
target-sparc/ldst_helper.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index f59293d..efdbabc 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -1643,6 +1643,18 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong
addr,
ret = env->scratch[i];
break;
}
+ case ASI_MMU: /* UA2005 Context ID registers */
+ switch ((addr >> 3) & 0x3) {
+ case 1:
+ ret = env->dmmu.mmu_primary_context;
+ break;
+ case 2:
+ ret = env->dmmu.mmu_secondary_context;
+ break;
+ default:
+ cpu_unassigned_access(cs, addr, true, false, 1, size);
+ }
+ break;
case ASI_DCACHE_DATA: /* D-cache data */
case ASI_DCACHE_TAG: /* D-cache tag access */
case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
@@ -2182,6 +2194,28 @@ void helper_st_asi(CPUSPARCState *env, target_ulong
addr, target_ulong val,
env->scratch[i] = val;
return;
}
+ case ASI_MMU: /* UA2005 Context ID registers */
+ {
+ switch ((addr >> 3) & 0x3) {
+ case 1:
+ env->dmmu.mmu_primary_context = val;
+ env->immu.mmu_primary_context = val;
+ /* can be optimized to only flush MMU_USER_PRIMARY_IDX
+ and MMU_KERNEL_PRIMARY_IDX entries */
+ tlb_flush(CPU(cpu), 1);
+ break;
+ case 2:
+ env->dmmu.mmu_secondary_context = val;
+ env->immu.mmu_secondary_context = val;
+ /* can be optimized to only flush MMU_USER_SECONDARY_IDX
+ and MMU_KERNEL_SECONDARY_IDX entries */
+ tlb_flush(CPU(cpu), 1);
+ break;
+ default:
+ cpu_unassigned_access(cs, addr, true, false, 1, size);
+ }
+ }
+ return;
case ASI_QUEUE: /* UA2005 CPU mondo queue */
case ASI_DCACHE_DATA: /* D-cache data */
case ASI_DCACHE_TAG: /* D-cache tag access */
--
2.7.2
