On 25 November 2010 11:46, Jan Kiszka <jan.kis...@siemens.com> wrote: > Am 24.11.2010 12:00, Alexander Graf wrote: >>>>> According to to the Intel IA-32 Software Developers Manual Vol 3 page >>>>> 290, the version should be 0x14 Pentium 4/Xeon CPUs anyway. >>>>> >>>>> Signed-off-by: Andrew de Quincey <a...@lidskialf.net> >>>>> >>>>> diff --git a/hw/apic.c b/hw/apic.c >>>>> index 5f4a87c..20304e0 100644 >>>>> --- a/hw/apic.c >>>>> +++ b/hw/apic.c >>>>> @@ -704,7 +704,7 @@ static uint32_t apic_mem_readl(void *opaque, >>>>> target_phys_addr_t addr) >>>>> val = s->id << 24; >>>>> break; >>>>> case 0x03: /* version */ >>>>> - val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ >>>>> + val = 0x14 | ((APIC_LVT_NB - 1) << 16); /* version 0x14 */ >>>> >>>> What exactly changed between the versions? Did new registers get >>>> introduced or subtle behavior change? Is there some proper documentation >>>> on the changed between the apic versions? >>> >>> I've been trying to find out; I'm still searching intel's docs to find >>> an 0x11 version to compare with :( >> >> Please try very hard. I haven't found anything myself either yet, but >> without a spec it's hard to justify these changes upstream :(. >> >>> The failure mode is that mac os X SL whines about the APIC being an >>> unexpected version (0x11) and it wants 0x14 as a minimum. >> >> Yup, I remember that issue. To really make this all useful, we also need to >> change the numbers in KVM though. > > Also, the version has to be set depending on the emulated CPU (even more > when there will be emulation differences).
Indeed. However, I've just been comparing the two docs (and yes it IS a huge pain in the bum!). The differences between the pentium/P6 (0x11 "APIC") and pentium4/xeon (0x14 "xAPIC") so far are: * LVT themal sensor 0xfee0330 is new in xAPIC -- this is already implemented in hw/apic.c * APIC ID register is 8 bits in xAPIC, 4 bits in APIC (top 4 are undefined) -- already 8 bit wide in hw/apic.c * APIC LVT count should be 4 in APIC, 6 in xAPIC -- already hardcoded to 6 in hw/apic.c * Spurious interrupt vector should have the lower 4 bits hardcoded to 1 in APIC -- this is not done in hw/apic.c - they're modifable. * Base address of LAPIC can be changed using an MSR in xAPIC, suppposedly not possible in APIC - hw/apic.c allows it no matter what. (I'm still reading) >From what I can see hw/apic.c already unconditionally supports all the features of the newer APICs anyway, and any changes are really just incremental tweaks. The other major difference between APIC and xAPIC is how they talk to each other in hardware: APIC has an APIC bus, xAPIC uses the system bus. I suspect this isn't a concern for emulated hardware though...
