On 01/10/2018 08:22 PM, Michael Clark wrote:
> This adds RISC-V into the build system enabling the following targets:
>
> - riscv32-softmmu
> - riscv64-softmmu
> - riscv32-linux-user
> - riscv64-linux-user
>
> This adds defaults configs for RISC-V, enables the build for the RISC-V
> CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
> script is updated to add the RISC-V ELF magic.
>
> +++ b/qapi-schema.json
> @@ -413,7 +413,7 @@
> # Since: 2.6
> ##
> { 'enum': 'CpuInfoArch',
> - 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] }
> + 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'riscv', 'other' ] }Still missing documentation that riscv was added in 2.12 (see my comments on v1). > --- /dev/null > +++ b/target/riscv/trace-events > @@ -0,0 +1 @@ > +# See docs/devel/tracing.txt for syntax documentation. > Do we really need this file if you don't have any traces yet? -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3266 Virtualization: qemu.org | libvirt.org
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