On Fri, Jan 12, 2018 at 4:47 AM, Richard Henderson < richard.hender...@linaro.org> wrote:
> On 01/10/2018 06:21 PM, Michael Clark wrote: > > TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU > > RISC-V code generator has complete coverage for the Base ISA v2.2, > > Privileged ISA v1.9.1 and Privileged ISA v1.10: > > > > - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 > > - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1 > > - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 > > > > Signed-off-by: Michael Clark <m...@sifive.com> > > --- > > target/riscv/instmap.h | 377 +++++++++ > > target/riscv/translate.c | 1982 ++++++++++++++++++++++++++++++ > ++++++++++++++++ > > 2 files changed, 2359 insertions(+) > > create mode 100644 target/riscv/instmap.h > > create mode 100644 target/riscv/translate.c > > While there is forward progress within translate.c, it would seem that > quite a > lot of my v1 comments are not yet addressed. > > Also, > > > + if (!riscv_has_ext(env, RVC)) { > > You may not access env in this way. Any code generation differences must > be > computable from either unchanging values on the cpu or tb->flags. MISA is > not > unchanging -- you allow runtime modification. > > Again, the partial patch I saw from Stefan would fix this. We'll definately address this in the next spin... Could you pleease forward me the patch or send me a pointer to where i might find it? Assuming we can use flags and misa is stored in the lower 26-bits then we change riscv_has_ext to take an int. e.g. riscv_has_ext(tb->flags, RVC))