On 02/08/2018 09:31 AM, Alex Bennée wrote:
> @@ -10727,40 +10727,152 @@ static void disas_simd_two_reg_misc(DisasContext
> *s, uint32_t insn)
> /* AdvSIMD [scalar] two register miscellaneous (FP16)
> *
> * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
> - * +---+---+---+---+--------+---+-------------+--------+-----+------+------+
> + * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
> * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
> - * +---+---+---+---+--------+---+-------------+--------+-----+------+------+
> + * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
> * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
> * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
> *
> - * ???While the group is listed with bit 28 always set to 1 this is not
> - * always the case.????
> - *
> - * This actually covers two groups,
> + * This actually covers two groups where scalar access is governed by
> + * bit 28. A bunch of the instructions (float to integral) only exist
> + * in the vector form and are un-allocated for the scalar decode. Also
> + * in the scalar decode Q is always 1.
> */
Fold this hunk back into previous patch.
>
> +
> + /* Check additional constraints for the scalar encoding */
> + if (is_scalar) {
> + if (!is_q) {
> + unallocated_encoding(s);
> + return;
> + }
> + /* FRINTxx is only in the vector form */
> + if (only_in_vector && is_scalar) {
> + unallocated_encoding(s);
> + return;
> + }
> + }
Testing is_scalar twice.
Otherwise it looks good.
r~
