On 03/27/2018 04:55 PM, Michael Clark wrote:
> This fixes a bug in the disassembler constraints used
> to lift instructions into pseudo-instructions, whereby
> addiw instructions are always lifted to sext.w instead
> of just lifting addiw with a zero immediate.
>
> An associated fix has been made to the metadata used to
> machine generate the disseasembler:
>
> https://github.com/michaeljclark/riscv-meta/
> commit/4a6b2f3898430768acfe201405224d2ea31e1477
>
> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <pal...@sifive.com>
> Cc: Peter Maydell <peter.mayd...@linaro.org>
> Signed-off-by: Michael Clark <m...@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
> ---
> disas/riscv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 3c17501..74ad16e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -600,7 +600,7 @@ static const rvc_constraint rvcc_mv[] = {
> rvc_imm_eq_zero, rvc_end };
> static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
> static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
> static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
> -static const rvc_constraint rvcc_sext_w[] = { rvc_rs2_eq_x0, rvc_end };
> +static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
> static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
> static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
> static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
>
