On 03/28/2018 03:55 AM, Michael Clark wrote: > This fixes a bug in the disassembler constraints used > to lift instructions into pseudo-instructions, whereby > addiw instructions are always lifted to sext.w instead > of just lifting addiw with a zero immediate. > > An associated fix has been made to the metadata used to > machine generate the disseasembler: > > https://github.com/michaeljclark/riscv-meta/ > commit/4a6b2f3898430768acfe201405224d2ea31e1477 > > Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> > Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> > Cc: Palmer Dabbelt <pal...@sifive.com> > Cc: Peter Maydell <peter.mayd...@linaro.org> > Signed-off-by: Michael Clark <m...@sifive.com> > --- > disas/riscv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
