On 22 June 2018 at 21:32, Aaron Lindsay <alind...@codeaurora.org> wrote: > Add an array for PMOVSSET so we only define it for v7ve+ platforms > > Signed-off-by: Aaron Lindsay <alind...@codeaurora.org> > --- > target/arm/helper.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 7d63bb2..5d83446 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -1293,9 +1293,17 @@ static void pmcntenclr_write(CPUARMState *env, const > ARMCPRegInfo *ri, > static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > + value &= pmu_counter_mask(env); > env->cp15.c9_pmovsr &= ~value; > }
This change doesn't look like it should be in this patch ? > > +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, > + uint64_t value) > +{ > + value &= pmu_counter_mask(env); > + env->cp15.c9_pmovsr |= value; > +} > + > static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > @@ -1645,6 +1653,23 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = { > REGINFO_SENTINEL > }; > > +static const ARMCPRegInfo pmovsset_cp_reginfo[] = { > + /* PMOVSSET is not implemented in v7 before v7ve */ > + { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = > 3, > + .access = PL0_RW, .accessfn = pmreg_access, > + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), > + .writefn = pmovsset_write, > + .raw_writefn = raw_write }, This should be marked ARM_CP_ALIAS, beacuse its underlying state in c9_pmovsr is just an alias into PMOVSR, and that register is handling reset and migration. > + { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, > + .access = PL0_RW, .accessfn = pmreg_access, > + .type = ARM_CP_ALIAS, > + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), > + .writefn = pmovsset_write, > + .raw_writefn = raw_write }, > + REGINFO_SENTINEL > +}; > + > static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > @@ -4996,6 +5021,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) > !arm_feature(env, ARM_FEATURE_PMSA)) { > define_arm_cp_regs(cpu, v7mp_cp_reginfo); > } > + if (arm_feature(env, ARM_FEATURE_V7VE)) { > + define_arm_cp_regs(cpu, pmovsset_cp_reginfo); > + } > if (arm_feature(env, ARM_FEATURE_V7)) { > /* v7 performance monitor control register: same implementor > * field as main ID register, and we implement only the cycle > -- thanks -- PMM