On 08/24/2018 12:44 PM, Craig Janeczek via Qemu-devel wrote: > +/* MXU General purpose registers moves. */ > +static inline void gen_load_mxu_gpr (TCGv t, int reg) > +{ > + if (reg == 0) > + tcg_gen_movi_tl(t, 0); > + else > + tcg_gen_mov_tl(t, mxu_gpr[reg-1]); > +} > + > +static inline void gen_store_mxu_gpr (TCGv t, int reg) > +{ > + if (reg != 0) > + tcg_gen_mov_tl(mxu_gpr[reg-1], t); > +} > + > /* Moves to/from shadow registers. */ > static inline void gen_load_srsgpr (int from, int to) > { > @@ -20742,6 +20767,11 @@ void mips_tcg_init(void) > fpu_fcr31 = tcg_global_mem_new_i32(cpu_env, > offsetof(CPUMIPSState, > active_fpu.fcr31), > "fcr31"); > + > + for (i = 0; i < 16; i++) > + mxu_gpr[i] = tcg_global_mem_new(cpu_env, > + offsetof(CPUMIPSState, > active_tc.mxu_gpr[i]), > + mxuregnames[i]); > }
You need to fix the ./scripts/checkpatch.pl errors. But otherwise the logic is ok. r~