On 10/6/18 2:45 PM, Emilio G. Cota wrote: > @@ -89,7 +89,7 @@ typedef uint64_t target_ulong; > * 0x18 (the offset of the addend field in each TLB entry) plus the offset > * of tlb_table inside env (which is non-trivial but not huge). > */ > -#define CPU_TLB_BITS \ > +#define MIN_CPU_TLB_BITS \ > MIN(8, \ > TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ > (NB_MMU_MODES <= 1 ? 0 : \
There's no point in this either, since the original constraint was due to the immediate offset into an add instruction. Now we're loading the base address from an array. The actual size of the tlb is immaterial now, since the size of the tlb does not affect the size of CPUArchState. r~
