Intel's upcoming processors will extend maximum linear address width to 57 bits, and introduce 5-level paging for CPU. Meanwhile, the platform will also extend the maximum guest address width for IOMMU to 57 bits, thus introducing the 5-level paging for 2nd level translation(See chapter 3 in Intel Virtualization Technology for Directed I/O).
This patch set extends the current logic to support a wider address width. A 5-level paging capable IOMMU(for 2nd level translation) can be rendered with configuration "device intel-iommu,x-aw-bits=57". Yu Zhang (3): intel-iommu: differentiate host address width from IOVA address width. intel-iommu: extend VTD emulation to allow 57-bit IOVA address width. intel-iommu: search iotlb for levels supported by the address width. --- Cc: "Michael S. Tsirkin" <m...@redhat.com> Cc: Igor Mammedov <imamm...@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelb...@gmail.com> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Richard Henderson <r...@twiddle.net> Cc: Eduardo Habkost <ehabk...@redhat.com> Cc: Peter Xu <pet...@redhat.com> hw/i386/acpi-build.c | 2 +- hw/i386/intel_iommu.c | 101 +++++++++++++++++++++++++++-------------- hw/i386/intel_iommu_internal.h | 13 ++++-- include/hw/i386/intel_iommu.h | 10 ++-- 4 files changed, 83 insertions(+), 43 deletions(-) -- 1.9.1
