On Fri, Nov 09, 2018 at 07:49:46PM +0800, Yu Zhang wrote: > A 5-level paging capable VM may choose to use 57-bit IOVA address width. > E.g. guest applications like DPDK prefer to use its VA as IOVA when > performing VFIO map/unmap operations, to avoid the burden of managing the > IOVA space.
Since you mentioned about DPDK... I'm just curious that whether have you tested the patchset with the 57bit-enabled machines with DPDK VA mode running in the guest? That would be something nice to mention in the cover letter if you have. [...] > @@ -3264,11 +3286,19 @@ static bool vtd_decide_config(IntelIOMMUState *s, > Error **errp) > } > } > > - /* Currently only address widths supported are 39 and 48 bits */ > + /* Currently address widths supported are 39, 48, and 57 bits */ > if ((s->aw_bits != VTD_AW_39BIT) && > - (s->aw_bits != VTD_AW_48BIT)) { > - error_setg(errp, "Supported values for x-aw-bits are: %d, %d", > - VTD_AW_39BIT, VTD_AW_48BIT); > + (s->aw_bits != VTD_AW_48BIT) && > + (s->aw_bits != VTD_AW_57BIT)) { > + error_setg(errp, "Supported values for x-aw-bits are: %d, %d, %d", > + VTD_AW_39BIT, VTD_AW_48BIT, VTD_AW_57BIT); > + return false; > + } > + > + if ((s->aw_bits == VTD_AW_57BIT) && > + !(host_has_la57() && guest_has_la57())) { > + error_setg(errp, "Do not support 57-bit DMA address, unless both " > + "host and guest are capable of 5-level paging.\n"); Is there any context (or pointer to previous discussions would work too) on explaining why we don't support some scenarios like host_paw=48,guest_paw=48,guest_gaw=57? Thanks, -- Peter Xu