On 1/21/19 10:51 AM, Peter Maydell wrote: > The SSE-200 gives each CPU a register bank to use to control its > L1 instruction cache. Put in an unimplemented-device stub for this. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > include/hw/arm/armsse.h | 1 + > hw/arm/armsse.c | 39 ++++++++++++++++++++++++++++++++++++++- > 2 files changed, 39 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
