Patchew URL: https://patchew.org/QEMU/20190307170440.3113-1-richard.hender...@linaro.org/
Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20190307170440.3113-1-richard.hender...@linaro.org Subject: [Qemu-devel] [PATCH v4 00/22] target/arm: Implement ARMv8.5-MemTag, system mode === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu * [new tag] patchew/20190307170440.3113-1-richard.hender...@linaro.org -> patchew/20190307170440.3113-1-richard.hender...@linaro.org Switched to a new branch 'test' 23fdebd210 target/arm: Enable MTE 3cf01953ff target/arm: Add allocation tag storage for system mode 494df9631b target/arm: Create a TLB entry for tag physical address space c3aea915ad target/arm: Create tagged ram when MTE is enabled f073d517ec target/arm: Cache the Tagged bit for a page in MemTxAttrs 7597116fed target/arm: Set PSTATE.TCO on exception entry 798d73e166 target/arm: Implement data cache set allocation tags 843a2c13d9 target/arm: Clean address for DC ZVA beff6e3558 target/arm: Implement the access tag cache flushes 79b5335524 target/arm: Implement the LDGM and STGM instructions ed9a915702 target/arm: Implement the STGP instruction 0143319256 target/arm: Implement LDG, STG, ST2G instructions 54357db2c5 target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY d72d1a0c0e target/arm: Implement the SUBP instruction ba50a7a99d target/arm: Implement the GMI instruction 09533e4e2c target/arm: Implement ADDG, SUBG instructions 593999e89a target/arm: Implement the IRG instruction 8306fd8033 target/arm: Suppress tag check for sp+offset c7edbeb68c target/arm: Add helper_mte_check{1, 2} 41eff3fb40 target/arm: Add MTE system registers 46e9777387 target/arm: Extract TCMA with ARMVAParameters e68d8da962 target/arm: Add MTE_ACTIVE to tb_flags === OUTPUT BEGIN === 1/22 Checking commit e68d8da9629d (target/arm: Add MTE_ACTIVE to tb_flags) 2/22 Checking commit 46e9777387ff (target/arm: Extract TCMA with ARMVAParameters) ERROR: spaces prohibited around that ':' (ctx:WxW) #70: FILE: target/arm/internals.h:962: + bool tcma : 1; ^ total: 1 errors, 0 warnings, 49 lines checked Patch 2/22 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 3/22 Checking commit 41eff3fb4034 (target/arm: Add MTE system registers) 4/22 Checking commit c7edbeb68c59 (target/arm: Add helper_mte_check{1, 2}) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #42: new file mode 100644 total: 0 errors, 1 warnings, 167 lines checked Patch 4/22 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 5/22 Checking commit 8306fd8033ee (target/arm: Suppress tag check for sp+offset) 6/22 Checking commit 593999e89a2f (target/arm: Implement the IRG instruction) 7/22 Checking commit 09533e4e2cda (target/arm: Implement ADDG, SUBG instructions) 8/22 Checking commit ba50a7a99db9 (target/arm: Implement the GMI instruction) 9/22 Checking commit d72d1a0c0eb1 (target/arm: Implement the SUBP instruction) 10/22 Checking commit 54357db2c561 (target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY) 11/22 Checking commit 014331925603 (target/arm: Implement LDG, STG, ST2G instructions) 12/22 Checking commit ed9a915702c2 (target/arm: Implement the STGP instruction) 13/22 Checking commit 79b53355245d (target/arm: Implement the LDGM and STGM instructions) 14/22 Checking commit beff6e355850 (target/arm: Implement the access tag cache flushes) 15/22 Checking commit 843a2c13d940 (target/arm: Clean address for DC ZVA) 16/22 Checking commit 798d73e16619 (target/arm: Implement data cache set allocation tags) 17/22 Checking commit 7597116fed95 (target/arm: Set PSTATE.TCO on exception entry) 18/22 Checking commit f073d517ec80 (target/arm: Cache the Tagged bit for a page in MemTxAttrs) 19/22 Checking commit c3aea915adb4 (target/arm: Create tagged ram when MTE is enabled) 20/22 Checking commit 494df9631b39 (target/arm: Create a TLB entry for tag physical address space) 21/22 Checking commit 3cf01953ff8b (target/arm: Add allocation tag storage for system mode) 22/22 Checking commit 23fdebd2106c (target/arm: Enable MTE) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20190307170440.3113-1-richard.hender...@linaro.org/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to patchew-de...@redhat.com