Windows ARM64 uses LLP64 model, which breaks current assumptions.

Signed-off-by: driver1998 <driver1...@foxmail.com>
---
 util/cacheinfo.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/util/cacheinfo.c b/util/cacheinfo.c
index 3cd080b83d..a815cb0722 100644
--- a/util/cacheinfo.c
+++ b/util/cacheinfo.c
@@ -107,7 +107,7 @@ static void sys_cache_info(int *isize, int *dsize)
 static void arch_cache_info(int *isize, int *dsize)
 {
     if (*isize == 0 || *dsize == 0) {
-        unsigned long ctr;
+        uintptr_t ctr;
 
         /* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
            but (at least under Linux) these are marked protected by the
@@ -120,6 +120,8 @@ static void arch_cache_info(int *isize, int *dsize)
         if (*dsize == 0) {
             *dsize = 4 << ((ctr >> 16) & 0xf);
         }
+
+        printf("%d %d\n", *isize, *dsize);
     }
 }
 
-- 
2.17.1


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