[Qemu-devel] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes

[Palmer Dabbelt]

From: Jonathan Behrens <jonat...@fintelia.io>

There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857

Signed-off-by: Jonathan Behrens <jonat...@fintelia.io>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Palmer Dabbelt <pal...@sifive.com>
---
 target/riscv/csr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0f51c7eae241..f9e2910643f8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -723,7 +723,9 @@ static int write_satp(CPURISCVState *env, int csrno, 
target_ulong val)
         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
             return -1;
         } else {
-            tlb_flush(CPU(riscv_env_get_cpu(env)));
+            if((val ^ env->satp) & SATP_ASID) {
+                tlb_flush(CPU(riscv_env_get_cpu(env)));
+            }
             env->satp = val;
         }
     }
-- 
2.21.0