From: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Palmer Dabbelt <pal...@sifive.com> Signed-off-by: Palmer Dabbelt <pal...@sifive.com> --- target/riscv/cpu_bits.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7180fccf54f9..945aa8dbb851 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -383,7 +383,7 @@ /* Privilege modes */ #define PRV_U 0 #define PRV_S 1 -#define PRV_H 2 +#define PRV_H 2 /* Reserved */ #define PRV_M 3 /* RV32 satp CSR field masks */ -- 2.21.0
