On Tue, 4 Jun 2019 at 22:08, Richard Henderson <richard.hender...@linaro.org> wrote: > > This changes the code generation for the tlb from e.g. > > ldr ip, [r6, #-0x10] > ldr r2, [r6, #-0xc] > and ip, ip, r4, lsr #8 > ldrd r0, r1, [r2, ip]! > ldr r2, [r2, #0x18] > > to > > ldrd r0, r1, [r6, #-0x10] > and r0, r0, r4, lsr #8 > ldrd r2, r3, [r1, r0]! > ldr r1, [r1, #0x18] > > for armv7 hosts. Rearranging the register allocation in > order to avoid overlap between the two ldrd pairs causes > the patch to be larger than it ordinarily would be. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks -- PMM
