On 6/17/19 10:53 AM, Peter Maydell wrote: > Thumb instructions in an IT block are set up to be conditionally > executed depending on a set of condition bits encoded into the IT > bits of the CPSR/XPSR. The architecture specifies that if the > condition bits are 0b1111 this means "always execute" (like 0b1110), > not "never execute"; we were treating it as "never execute". (See > the ConditionHolds() pseudocode in both the A-profile and M-profile > Arm ARM.) > > This is a bit of an obscure corner case, because the only legal > way to get to an 0b1111 set of condbits is to do an exception > return which sets the XPSR/CPSR up that way. An IT instruction > which encodes a condition sequence that would include an 0b1111 is > UNPREDICTABLE, and for v8A the CONSTRAINED UNPREDICTABLE choices > for such an IT insn are to NOP, UNDEF, or treat 0b1111 like 0b1110. > Add a comment noting that we take the latter option. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/translate.c | 15 +++++++++++++-- > 1 file changed, 13 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
