For completeness let's add Zifencei and Zicsr as command line options, even though they can't be disabled at the moment.
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu.c | 9 +++++++++ target/riscv/cpu.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5af1c9b38c..53cf8607f7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -409,6 +409,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_misa(env, RVXLEN | target_misa); } + if (!cpu->cfg.ext_ifencei) { + warn_report("QEMU does not support disabling Zifencei"); + } + if (!cpu->cfg.ext_icsr) { + warn_report("QEMU does not support disabling Zicsr"); + } + riscv_cpu_register_gdb_regs_for_features(cs); qemu_init_vcpu(cs); @@ -441,6 +448,8 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), + DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), + DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 786f620564..b4c212dfcf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -222,6 +222,8 @@ typedef struct RISCVCPU { bool ext_s; bool ext_u; bool ext_counters; + bool ext_ifencei; + bool ext_icsr; char *priv_spec; char *user_spec; -- 2.22.0