On 6/18/19 3:31 AM, Alistair Francis wrote: > Restructure the deprecated CPUs to make it clear in the code that these > are depreated. They are already marked as deprecated in > qemu-deprecated.texi. There are no functional changes. > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > --- > target/riscv/cpu.c | 18 ++++++++++-------- > target/riscv/cpu.h | 13 +++++++------ > 2 files changed, 17 insertions(+), 14 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0632ac08cf..a4dd7ae6fc 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -558,18 +558,20 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), > #if defined(TARGET_RISCV32) > DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, > rv32gcsu_priv1_09_1_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, > rv32gcsu_priv1_10_0_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init) > + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, > rv32gcsu_priv1_10_0_cpu_init), > + /* Depreacted */
"Deprecated" in patch subject and here ;) > + DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, > rv32gcsu_priv1_09_1_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init) > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, > rv64gcsu_priv1_09_1_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, > rv64gcsu_priv1_10_0_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), > - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init) > + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, > rv64gcsu_priv1_10_0_cpu_init), > + /* Deprecated */ > + DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, > rv64gcsu_priv1_09_1_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init) > #endif > }; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b47cde5017..1668d12018 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -35,16 +35,17 @@ > #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 > RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") > -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 > RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") > -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU > RISCV_CPU_TYPE_NAME("rv32imacu-nommu") > -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 > RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") > -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 > RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") > -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU > RISCV_CPU_TYPE_NAME("rv64imacu-nommu") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") > +/* Deprecated */ > +#define TYPE_RISCV_CPU_RV32IMACU_NOMMU > RISCV_CPU_TYPE_NAME("rv32imacu-nommu") > +#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 > RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") > +#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 > RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") > +#define TYPE_RISCV_CPU_RV64IMACU_NOMMU > RISCV_CPU_TYPE_NAME("rv64imacu-nommu") > +#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 > RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") > +#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 > RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") > > #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) > #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) >