On 7/11/19 5:32 AM, Richard Henderson wrote:
> On 7/10/19 8:29 PM, Jan Bobek wrote:
>>>> +# Arithmetic Instructions
>>>> +PADDB MMX 00001111 11111100 !emit { modrm(); mem(size =>
>>>> 8); }
>>>> +PADDW MMX 00001111 11111101 !emit { modrm(); mem(size =>
>>>> 8); }
>>>> +PADDD MMX 00001111 11111110 !emit { modrm(); mem(size =>
>>>> 8); }
>>>> +PADDQ MMX 00001111 11010100 !emit { modrm(); mem(size =>
>>>> 8); }
>>
>> Not this one, at least according to the Intel docs:
>>
>> NP 0F D4 /r: PADDQ mm, mm/m64 (MMX)
>> 66 0F D4 /r: PADDQ xmm1, xmm2/m128 (SSE2)
>>
>> The SSE2 version is added in a later patch.
>
> That's not how I read the Intel docs.
>
> In the CPUID feature flag column of the MMX PADDQ, I see SSE2. While the insn
> affects the mmx registers, it was not added with the original MMX instruction
> set.
I know what you mean; for example, PSUBQ is like that. I know about
these kind of instructions because "{name}_{enc}" does not form a
unique key, and risugen would complain about that. That's why there is
PSUBQ_mm and PSUBQ in the final x86.risu file.
However, I downloaded a fresh copy of Intel SDM off the Intel website
this morning (just to make sure) and in Volume 2B, Section "4.3
Instructions (M-U)," page 4-208 titled "PADDB/PADDW/PADDD/PADDQ—Add
Packed Integers," there's the NP 0F D4 /r PADDQ mm, mm/m64 instruction
in the 4th row, and the CPUID column says MMX. On the other hand, I
can't find it in the Volume 1, Section 5.4 "MMX(tm) Instructions," or
in Vol. 1, Chapter 9 "Programming with Intel(R) MMX(tm) Technology,"
so it's a bit confusing.
If you know for a fact that it didn't come until SSE2 and the manual
is wrong, I will change it.
-Jan
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