On 7/11/19 9:57 AM, Richard Henderson wrote: > On 7/11/19 3:29 PM, Jan Bobek wrote: >> However, I downloaded a fresh copy of Intel SDM off the Intel website >> this morning (just to make sure) and in Volume 2B, Section "4.3 >> Instructions (M-U)," page 4-208 titled "PADDB/PADDW/PADDD/PADDQ—Add >> Packed Integers," there's the NP 0F D4 /r PADDQ mm, mm/m64 instruction >> in the 4th row, and the CPUID column says MMX. On the other hand, I >> can't find it in the Volume 1, Section 5.4 "MMX(tm) Instructions," or >> in Vol. 1, Chapter 9 "Programming with Intel(R) MMX(tm) Technology," >> so it's a bit confusing. >> >> If you know for a fact that it didn't come until SSE2 and the manual >> is wrong, I will change it. > > Interesting. I see what you see in > > 253665-069US January 2019 > > but I first looked at > > 325462-058US April 2016 > > which definitely has this marked as SSE2. > > In the 2019 version, "5.6.3 SSE2 128-Bit SIMD Integer Instructions" is the > first mention of PADDQ. Whereas "5.4.3 MMX Packed Arithmetic Instructions" > mentions PADD{B,W,D} but not Q. > > I tend to think that this is a bug in the current manual. > > Checking in binutils I see > >> paddq, 2, 0x660fd4, None, 2, CpuSSE2, >> Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { >> RegXMM|Unspecified|BaseIndex, RegXMM } >> paddq, 2, 0xfd4, None, 2, CpuSSE2, >> Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { >> Qword|Unspecified|BaseIndex|RegMMX, RegMMX } > > and both contain CpuSSE2. If you like, I could run this by one of the Intel > GCC > folk to be sure.
I think this is convincing enough for me; it was a good idea to check binutils! I find it interesting that they'd get it wrong in a more recent version of the manual, though. -Jan
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