The TIMA MMIO space is shared among the chips and to identify the chip from which the access is being done, the PowerBUS uses a chip field in the load/store messages. QEMU does not model these messages, so instead, we extract the chip id from the CPU PIR and do a lookup at the machine level to fetch the targeted interrupt controller.
Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify this process in pnv_xive_get_tctx(). The latter will be removed in the subsequent patches but the same principle will be kept. Signed-off-by: Cédric Le Goater <c...@kaod.org> --- include/hw/ppc/pnv.h | 13 +++++++++++++ hw/intc/pnv_xive.c | 40 +++++++++++++++++++++++----------------- 2 files changed, 36 insertions(+), 17 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index fb123edc4e5a..72b5cbb606b5 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -182,6 +182,19 @@ static inline bool pnv_is_power9(PnvMachineState *pnv) return pnv_chip_is_power9(pnv->chips[0]); } +static inline PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) +{ + int i; + + for (i = 0; i < pnv->num_chips; i++) { + PnvChip *chip = pnv->chips[i]; + if (chip->chip_id == chip_id) { + return chip; + } + } + return NULL; +} + #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 6f53a2abbb6a..e598857359d8 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -464,31 +464,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, return count; } +/* + * The TIMA MMIO space is shared among the chips and to identify the + * chip from which the access is being done, we extract the chip id + * from the PIR. + */ +static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) +{ + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + PnvChip *chip; + PnvXive *xive; + + chip = pnv_get_chip(pnv, cpu_chip_id(cpu)); + assert(chip); + xive = &PNV9_CHIP(chip)->xive; + + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + xive_error(xive, "IC: CPU %x is not enabled", cpu_pir(cpu)); + } + return xive; +} + static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); - PnvXive *xive = NULL; - CPUPPCState *env = &cpu->env; - int pir = env->spr_cb[SPR_PIR].default_value; + PnvXive *xive = pnv_xive_tm_get_xive(cpu); - /* - * Perform an extra check on the HW thread enablement. - * - * The TIMA is shared among the chips and to identify the chip - * from which the access is being done, we extract the chip id - * from the PIR. - */ - xive = pnv_xive_get_ic((pir >> 8) & 0xf); if (!xive) { return NULL; } - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) { - xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir); - } - - return tctx; + return XIVE_TCTX(pnv_cpu_state(cpu)->intc); } /* -- 2.21.0