On 31/07/2019 16:12, Cédric Le Goater wrote: > The CAM line matching on the PowerNV machine now scans all chips of > the system and all CPUs of a chip to find a dispatched NVT in the > thread contexts. > > As there is now easy way to loop on the CPUs belonging to a chip, the > PowerNV handler loops on all CPUs and filter out the external CPUs. > > Fixes: af53dbf6227a ("ppc/xive: introduce a simplified XIVE presenter") > Signed-off-by: Cédric Le Goater <c...@kaod.org> > --- > hw/intc/pnv_xive.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++ > hw/ppc/pnv.c | 32 +++++++++++++++++++ > 2 files changed, 108 insertions(+) > > diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c > index ff1226485983..183798b81496 100644 > --- a/hw/intc/pnv_xive.c > +++ b/hw/intc/pnv_xive.c > @@ -390,6 +390,80 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t > blk, uint32_t idx, > return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); > } > > +static int cpu_pir(PowerPCCPU *cpu) > +{ > + CPUPPCState *env = &cpu->env; > + return env->spr_cb[SPR_PIR].default_value; > +} > + > +static int cpu_chip_id(PowerPCCPU *cpu) > +{ > + int pir = cpu_pir(cpu); > + return (pir >> 8) & 0x7f; > +} > + > +static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu) > +{ > + int pir = cpu_pir(cpu); > + int thrd_id = pir & 0x7f; > + > + return xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(thrd_id); > +} > + > +static bool pnv_xive_is_ignored(PnvChip *chip, CPUState *cs) > +{ > + return chip->chip_id != cpu_chip_id(POWERPC_CPU(cs)); > +} > + > +#define PNV_CHIP_CPU_FOREACH(chip, cs) \ > + CPU_FOREACH(cs) \ > + if (pnv_xive_is_ignored(chip, cs)) {} else
patchew will complain here but I think we can consider it as an exception since it is inspired from the macros in migration/ram.c ? Thanks, C.