On 9/16/19 1:02 PM, Paul A. Clarke wrote: > From: "Paul A. Clarke" <p...@us.ibm.com> > > ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) > instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. > This patch adds support for 'mffsce' instruction. > > 'mffsce' is identical to 'mffs', except that it also clears the exception > enable bits in the FPSCR. > > On CPUs without support for 'mffsce' (below ISA 3.0), the > instruction will execute identically to 'mffs'. > > Signed-off-by: Paul A. Clarke <p...@us.ibm.com> > --- > v2: no changes. > > target/ppc/translate/fp-impl.inc.c | 30 ++++++++++++++++++++++++++++++ > target/ppc/translate/fp-ops.inc.c | 2 ++ > 2 files changed, 32 insertions(+)
Didn't I already give a Reviewed-by: Richard Henderson <richard.hender...@linaro.org> for this? r~
