On Tue, Sep 17, 2019 at 04:49:56PM -0500, Paul Clarke wrote: > On 9/17/19 3:46 PM, Richard Henderson wrote: > > On 9/16/19 1:02 PM, Paul A. Clarke wrote: > >> From: "Paul A. Clarke" <p...@us.ibm.com> > >> > >> ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) > >> instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. > >> This patch adds support for 'mffsce' instruction. > >> > >> 'mffsce' is identical to 'mffs', except that it also clears the exception > >> enable bits in the FPSCR. > >> > >> On CPUs without support for 'mffsce' (below ISA 3.0), the > >> instruction will execute identically to 'mffs'. > >> > >> Signed-off-by: Paul A. Clarke <p...@us.ibm.com> > >> --- > >> v2: no changes. > >> > >> target/ppc/translate/fp-impl.inc.c | 30 ++++++++++++++++++++++++++++++ > >> target/ppc/translate/fp-ops.inc.c | 2 ++ > >> 2 files changed, 32 insertions(+) > > > > Didn't I already give a > > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> > > > > for this? > > You did. Sorry for the confusion. I wasn't sure whether to resend > or not, given the dependence on the other patch and David said he > would be waiting for the respin.
Please resend for my convenience, but you can fold in the previously received R-b lines, assuming the patch isn't changing. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
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