On Saturday, November 30, 2019, Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Wednesday, November 27, 2019, Michael Rolnik <mrol...@gmail.com> wrote:
>
> +
>> +
>> +/*
>> + * Performs the logical AND between the contents of register Rd and
>> register
>> + * Rr and places the result in the destination register Rd.
>> + */
>> +static bool trans_AND(DisasContext *ctx, arg_AND *a)
>> +{
>> + TCGv Rd = cpu_r[a->rd];
>> + TCGv Rr = cpu_r[a->rr];
>> + TCGv R = tcg_temp_new_i32();
>> +
>> + /* op */
>> + tcg_gen_and_tl(R, Rd, Rr); /* Rd = Rd and Rr */
>> +
>> + /* Vf */
>> + tcg_gen_movi_tl(cpu_Vf, 0); /* Vf = 0 */
>> +
>> + /* Zf */
>> + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf = R == 0 */
>> +
>> + gen_ZNSf(R);
>> +
>> + /* R */
>> + tcg_gen_mov_tl(Rd, R);
>> +
>> + tcg_temp_free_i32(R);
>> +
>> + return true;
>> +}
>> +
>> +
>>
>
> According to specs:
>
> http://ww1.microchip.com/downloads/en/devicedoc/atmel-42505-8-bit-avr-
> microcontrollers-attiny102-attiny104_datasheet.pdf
>
> ... the chips in question have cores with 16 GPRs (that correspond to GPRs
> R16-R31 of more common AVR cores with 32 GPRs).
>
>
There are more examples;
http://ww1.microchip.com/downloads/en/DeviceDoc/atmel-8127-avr-8-bit-microcontroller-attiny4-attiny5-attiny9-attiny10_datasheet.pdf
Also ATtiny20, ATtiny40.
How do you handle such cores?
>
> I don't see here anything preventing usage of all 32 GPRs, resulting, of
> course, in an inaccurate emulation.
>
> Thanks,
> Aleksandar
>
