On 8/28/20 11:33 AM, Peter Maydell wrote:
> Convert the Neon floating-point VMUL, VMLA and VMLS to use gvec,
> and use this to implement fp16 support.
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
> + /* a->vm is M:Vm, which encodes both register and index */
> + idx = extract32(a->vm, a->size + 2, 2);
> + a->vm = extract32(a->vm, 0, a->size + 2);
I know this is what the current code does, but I tend to think that this is
better done in decode. E.g.
# SVE floating-point multiply (indexed)
FMUL_zzx 01100100 0.1 .. rm:3 001000 rn:5 rd:5 \
index=%index3_22_19 esz=1
FMUL_zzx 01100100 101 index:2 rm:3 001000 rn:5 rd:5 \
esz=2
FMUL_zzx 01100100 111 index:1 rm:4 001000 rn:5 rd:5 \
esz=3
r~
