Hi, Richard, On Wed, Sep 16, 2020 at 11:15 PM Richard Henderson <richard.hender...@linaro.org> wrote: > > On 9/15/20 7:12 PM, Huacai Chen wrote: > > + case OPC_GSLQ: > > + gen_base_offset_addr(ctx, t0, rs, lsq_offset); > > + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ | > > + ctx->default_tcg_memop_mask); > > + gen_store_gpr(t0, rt); > > + gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); > > + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ | > > + ctx->default_tcg_memop_mask); > > + gen_store_gpr(t0, lsq_rt1); > > If rs == rt, this will compute the wrong address for the second load. > > Either avoid storing t0 back to rt until both loads are complete, or retain > the > address temporary and simply add 8 between the two loads. OK, this will be improved in V10.
> > > r~
