On 11/19/20 3:56 PM, Peter Maydell wrote: > The FPDSCR register has a similar layout to the FPSCR. In v8.1M it > gains new fields FZ16 (if half-precision floating point is supported) > and LTPSIZE (always reads as 4). Update the reset value and the code > that handles writes to this register accordingly. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/cpu.h | 5 +++++ > hw/intc/armv7m_nvic.c | 9 ++++++++- > target/arm/cpu.c | 3 +++ > 3 files changed, 16 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
