From: Kito Cheng <kito.ch...@sifive.com> Signed-off-by: Kito Cheng <kito.ch...@sifive.com> Signed-off-by: Frank Chang <frank.ch...@sifive.com> --- target/riscv/insn32-64.decode | 4 ++ target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvb.c.inc | 58 +++++++++++++++++++++++++ target/riscv/translate.c | 13 ++++++ 4 files changed, 79 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index e2490f791b7..6d017c70c74 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -98,7 +98,11 @@ sbsetw 0010100 .......... 001 ..... 0111011 @r sbclrw 0100100 .......... 001 ..... 0111011 @r sbinvw 0110100 .......... 001 ..... 0111011 @r sbextw 0100100 .......... 101 ..... 0111011 @r +slow 0010000 .......... 001 ..... 0111011 @r +srow 0010000 .......... 101 ..... 0111011 @r sbsetiw 0010100 .......... 001 ..... 0011011 @sh5 sbclriw 0100100 .......... 001 ..... 0011011 @sh5 sbinviw 0110100 .......... 001 ..... 0011011 @sh5 +sloiw 0010000 .......... 001 ..... 0011011 @sh5 +sroiw 0010000 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c697ff5c867..78ce4b11097 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -615,8 +615,12 @@ sbset 0010100 .......... 001 ..... 0110011 @r sbclr 0100100 .......... 001 ..... 0110011 @r sbinv 0110100 .......... 001 ..... 0110011 @r sbext 0100100 .......... 101 ..... 0110011 @r +slo 0010000 .......... 001 ..... 0110011 @r +sro 0010000 .......... 101 ..... 0110011 @r sbseti 00101. ........... 001 ..... 0010011 @sh sbclri 01001. ........... 001 ..... 0010011 @sh sbinvi 01101. ........... 001 ..... 0010011 @sh sbexti 01001. ........... 101 ..... 0010011 @sh +sloi 00100. ........... 001 ..... 0010011 @sh +sroi 00100. ........... 101 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 43e9b670f73..11b5439e703 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -155,6 +155,40 @@ static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a) return gen_shifti(ctx, a, &gen_sbext); } +static bool trans_slo(DisasContext *ctx, arg_slo *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, &gen_slo); +} + +static bool trans_sloi(DisasContext *ctx, arg_sloi *a) +{ + REQUIRE_EXT(ctx, RVB); + + if (a->shamt >= TARGET_LONG_BITS) { + return false; + } + + return gen_shifti(ctx, a, &gen_slo); +} + +static bool trans_sro(DisasContext *ctx, arg_sro *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, &gen_sro); +} + +static bool trans_sroi(DisasContext *ctx, arg_sroi *a) +{ + REQUIRE_EXT(ctx, RVB); + + if (a->shamt >= TARGET_LONG_BITS) { + return false; + } + + return gen_shifti(ctx, a, &gen_sro); +} + { /* RV64-only instructions */ #ifdef TARGET_RISCV64 @@ -231,4 +265,28 @@ static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a) return gen_shiftw(ctx, a, &gen_sbext); } +static bool trans_slow(DisasContext *ctx, arg_slow *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, &gen_slo); +} + +static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, &gen_slo); +} + +static bool trans_srow(DisasContext *ctx, arg_srow *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, &gen_sro); +} + +static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, &gen_sro); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ca176709674..0c00d20ab1b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -797,6 +797,19 @@ static void gen_sbext(TCGv ret, TCGv arg1, TCGv shamt) tcg_gen_andi_tl(ret, ret, 1); } +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_not_tl(ret, arg1); + tcg_gen_shl_tl(ret, ret, arg2); + tcg_gen_not_tl(ret, ret); +} + +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_not_tl(ret, arg1); + tcg_gen_shr_tl(ret, ret, arg2); + tcg_gen_not_tl(ret, ret); +} #ifdef TARGET_RISCV64 -- 2.17.1