On Thu, Dec 17, 2020 at 2:23 AM Alistair Francis <alistair.fran...@wdc.com> wrote: > > Instead of using string compares to determine if a RISC-V machine is > using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids > us having to maintain a list of CPU names to compare against. > > This commit also fixes the name of the function to match the > riscv_cpu_is_32bit() function. > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > --- > include/hw/riscv/boot.h | 8 +++++--- > hw/riscv/boot.c | 31 ++++++++++--------------------- > hw/riscv/sifive_u.c | 10 +++++----- > hw/riscv/spike.c | 8 ++++---- > hw/riscv/virt.c | 9 +++++---- > 5 files changed, 29 insertions(+), 37 deletions(-) > > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index b6d37a91d6..20ff5fe5e5 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -22,10 +22,11 @@ > > #include "exec/cpu-defs.h" > #include "hw/loader.h" > +#include "hw/riscv/riscv_hart.h" > > -bool riscv_is_32_bit(MachineState *machine); > +bool riscv_is_32bit(RISCVHartArrayState harts); > > -target_ulong riscv_calc_kernel_start_addr(MachineState *machine, > +target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts, > target_ulong firmware_end_addr); > target_ulong riscv_find_and_load_firmware(MachineState *machine, > const char > *default_machine_firmware, > @@ -41,7 +42,8 @@ target_ulong riscv_load_kernel(const char *kernel_filename, > hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, > uint64_t kernel_entry, hwaddr *start); > uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); > -void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr saddr, > +void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState > harts, > + hwaddr saddr, > hwaddr rom_base, hwaddr rom_size, > uint64_t kernel_entry, > uint32_t fdt_load_addr, void *fdt); > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 6bce6fb485..83586aef41 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -33,28 +33,16 @@ > > #include <libfdt.h> > > -bool riscv_is_32_bit(MachineState *machine) > +bool riscv_is_32bit(RISCVHartArrayState harts) > { > - /* > - * To determine if the CPU is 32-bit we need to check a few different > CPUs. > - * > - * If the CPU starts with rv32 > - * If the CPU is a sifive 3 seriries CPU (E31, U34) > - * If it's the Ibex CPU > - */ > - if (!strncmp(machine->cpu_type, "rv32", 4) || > - (!strncmp(machine->cpu_type, "sifive", 6) && > - machine->cpu_type[8] == '3') || > - !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) { > - return true; > - } else { > - return false; > - } > + RISCVCPU hart = harts.harts[0];
What happens if something like ARM big.LITTLE needs to be supported on RISC-V? > + > + return riscv_cpu_is_32bit(&hart.env); > } > [snip] Regards, Bin