On Thu, 14 Jan 2021 at 14:48, Peter Maydell <peter.mayd...@linaro.org> wrote: > > On Thu, 14 Jan 2021 at 11:24, Maxim Uvarov <maxim.uva...@linaro.org> wrote: > > > > On Thu, 14 Jan 2021 at 14:22, Maxim Uvarov <maxim.uva...@linaro.org> wrote: > > > Does that mean that in that case you need all regions to be 64k > > > aligned? I mean secure and non-secure. > > > Has anybody tested 64k pages under qemu? > > > [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 } > > > [VIRT_UART] = { 0x09000000, 0x00001000 }, > > > [VIRT_RTC] = { 0x09010000, 0x00001000 }, > > > [VIRT_GPIO] = { 0x09030000, 0x00001000 }, > > > [VIRT_SECURE_GPIO] = { 0x09031000, 0x00001000 }, > > > [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, > > > [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, > > > > > > Maxim. > > > > I.e. I see comment: > > * Note that devices should generally be placed at multiples of 0x10000, > > * to accommodate guests using 64K pages. > > */ > > > > but it's not clear why UART, RTC and GPIO is not aligned to 64k. > > Er, 0x09000000, 0x09010000 and 0x09030000 are all 64K aligned addresses. > > thanks > -- PMM
thanks, will send an updated version.