Hi Peter, On 2/2/21 6:54 PM, Peter Maydell wrote: > Mostly just bug fixes. The important one here is > hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register > which fixes a buffer overrun that's a security issue if you're running > KVM on Arm with kernel-irqchip=off (which hopefully nobody is doing in > a security context, because kernel-irqchip=on is the default and the > sensible choice for performance).
FYI Prasad mentioned a CVE was requested: https://www.mail-archive.com/qemu-devel@nongnu.org/msg778659.html As you said it is an odd configuration, I am not sure it is worth to wait for the CVE number to add it to the commit (which helps downstream distributions tracking these). [updating] Just got detail from Prasad on IRC, it usually takes ~1 day to get the CVE number assigned, so maybe worth postponing this until tomorrow. Prasad, can you reply to this message ASAP once you get the number? Thanks, Phil. > -- PMM > > The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e: > > Merge remote-tracking branch > 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01 > 16:28:00 +0000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20210202-1 > > for you to fetch changes up to 14657850c9cc10948551fbb884c30eb5a3a7370a: > > hw/arm: Display CPU type in machine description (2021-02-02 17:53:44 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * hw/intc/arm_gic: Allow to use QTest without crashing > * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled > * hw/char/exynos4210_uart: Fix missing call to report ready for input > * hw/arm/smmuv3: Fix addr_mask for range-based invalidation > * hw/ssi/imx_spi: Fix various minor bugs > * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register > * hw/arm: Add missing Kconfig dependencies > * hw/arm: Display CPU type in machine description > > ---------------------------------------------------------------- > Bin Meng (5): > hw/ssi: imx_spi: Use a macro for number of chip selects supported > hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() > hw/ssi: imx_spi: Round up the burst length to be multiple of 8 > hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic > hw/ssi: imx_spi: Correct tx and rx fifo endianness > > Iris Johnson (2): > hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled > hw/char/exynos4210_uart: Fix missing call to report ready for input > > Philippe Mathieu-Daudé (12): > hw/intc/arm_gic: Allow to use QTest without crashing > hw/ssi: imx_spi: Remove pointless variable initialization > hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value > hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled > hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled > hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register > hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ > hw/arm/exynos4210: Add missing dependency on OR_IRQ > hw/arm/xlnx-versal: Versal SoC requires ZDMA > hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals > hw/net/can: ZynqMP CAN device requires PTIMER > hw/arm: Display CPU type in machine description > > Xuzhou Cheng (1): > hw/ssi: imx_spi: Disable chip selects when controller is disabled > > Zenghui Yu (1): > hw/arm/smmuv3: Fix addr_mask for range-based invalidation > > include/hw/ssi/imx_spi.h | 5 +- > hw/arm/digic_boards.c | 2 +- > hw/arm/microbit.c | 2 +- > hw/arm/netduino2.c | 2 +- > hw/arm/netduinoplus2.c | 2 +- > hw/arm/orangepi.c | 2 +- > hw/arm/smmuv3.c | 4 +- > hw/arm/stellaris.c | 4 +- > hw/char/exynos4210_uart.c | 7 ++- > hw/intc/arm_gic.c | 5 +- > hw/ssi/imx_spi.c | 153 > +++++++++++++++++++++++++++++----------------- > hw/Kconfig | 1 + > hw/arm/Kconfig | 5 ++ > hw/dma/Kconfig | 3 + > hw/dma/meson.build | 2 +- > 15 files changed, 130 insertions(+), 69 deletions(-) >