On Wed, 3 Feb 2021 at 16:56, Mike Nawrocki <michael.nawro...@gtri.gatech.edu> wrote: > > The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them > to 1 only when there is no support for AArch32 at EL1 or above. > > The reset value will be 0x30 only if the CPU is AArch64-only; if there > is support for AArch32 at EL1 or above, it will be reset to 0. > > Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32 > is supported at EL1 or above. > > Signed-off-by: Mike Nawrocki <michael.nawro...@gtri.gatech.edu> > --- > target/arm/cpu.h | 5 +++++ > target/arm/helper.c | 16 ++++++++++++++-- > 2 files changed, 19 insertions(+), 2 deletions(-)
Applied to target-arm.next, thanks. -- PMM
