On Fri, 5 Mar 2021 at 20:22, Keith Packard <kei...@keithp.com> wrote: > > Peter Maydell <peter.mayd...@linaro.org> writes: > > > Also, you don't seem to have the correct "is the CPU in > > 32-bit or 64-bit mode" test here: you cannot rely on target_ulong > > being the right size, you must make a runtime check. > > Do you mean whether a dual aarch64/arm core is in arm or aarch64 mode, > or whether an aarch64 is running a 32-bit ABI?
For semihosting for Arm what matters is "what state is the core in at the point where it makes the semihosting SVC/HLT/etc insn?". How does RISCV specify it? thanks -- PMM
